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Figure 1: Schematic for the ADF7012 Test Board.
Figure 2: PCB Layout for the ADF7012 Test Board.

The ADF7012 is a single-chip, ASK/FSK transmitter IC supporting multiple modulation types, and integrating a fractional-N PLL, allowing transmit frequencies to be selected by an external microcontroller.[1] Similarly to the MICRF112 discussed previously, the ADF7012 is designed for digital modulations via clock and data pins on the device, and the carrier is generated using a PLL, with a crystal or oscillator as a reference. The device is capable of +14dBm output power, and covers a frequency range of 75MHz to 1GHz via the PLL and output divider. The test board provides a low pass filter, access to the SPI bus, and control voltage for an external 20MHz VCXO, used as the reference. The schematic for this test board is shown in Figure 1, and the board is shown in Figure 2 below.

Hand-Etched PCB

The first PCB order, containing the PCBs for the ADF7012 prototype was lost in the mail, with the replacements due 2-3 weeks after 2/12/2012. To lessen the impact of this delay, I hand-etched a slightly modified copy of the ADF7012 PCB. The only modification necessary was to increase the drill size of the vias from 20 to 30 mils, in order to fit the smallest drill bit I had available. The design was first printed on paper and taped to the board. Two holes were drilled as reference to align the top and bottom layers. The PCB artwork was then printed for the top side (mirrored) and bottom side on Staples Photo Basic paper, recommended for the toner transfer method of etching PCBs. Once the toner was transferred to the copper board, the paper was removed and the board was etched using ferric chloride. After etching, the board was cleaned and the top and bottom layers were connected using small gauge wire soldered to the via pads. These solder joints were then ground down to prevent interference with components placed above. The board was electrically tested to ensure no shorts were present, and the components were soldered. The board was then electrically tested after soldering and a short at the loop filter output was corrected.

PCB/Construction Photos (Handmade)

PCB/Construction Photos (Commercial)

Bill of Materials

Part Quantity Unit Cost Total Cost Source
SMA Male Connector 1/5 $2.51 $0.50 Dealextreme
ADF7012 1 $4.28 $4.28 Digi-Key
20MHz VCXO 1 $3.63 $3.63 Digi-Key
0603 Capacitor 15 $0.0096 $0.14 eBay - mib_instruments
1206 Tantalum Capacitor 1 $0.44 $0.44 Digi-Key
0603 Resistor 3 $0.00294 $0.01 eBay - mib_instruments
0603 Inductor (Taiyo Yuden HK Series) 4 $0.064 $0.26 Digi-Key
Male Header 7 $0.01 $0.07 eBay
PCB 1.4"x0.7"/3 $5.00 $1.63 Laen's PCB
Total Unit Cost $10.96


Programming the device was achieved using an MSP430 Launchpad with a MSP430G2553 microcontroller, using the USCI module in SPI mode, and code written to send 24 and 32 bit messages to the ADF7012. A spreadsheet was created containing the four configuration registers, broken down to individual options (e.g. R divider, N divider values, PA on/off). The working configuration is shown below:

Configuration register worksheet and resulting values.

Once the device was verified functional, a test program was written to transmit morse code, using FM generated by modulating the VCO by a 200mV 400Hz signal from a function generator.

The spreadsheet for the configuration of registers can be found here:

The Morse code example program for MSP430G2553 can be found here:

Debugging and Development Process

The first step in verifying the board worked was applying power after checking for shorts, and verifying the quiescent current of the device. The VCXO output was verified with an oscilloscope to ensure the proper 20MHz output. The SPI code was tested first on the oscilloscope and with an SPI graphic LCD to ensure no software errors. The ADF7012 was then loaded with initial values, and the MUXOUT pin was selected to output a divided reference clock. The divider was modified to ensure the SPI code was working. The MUXOUT pin was then selected to output the R and N divider outputs. These were found to be different frequencies, indicating the PLL was not locking or operating correctly. The input and output of the loop filter were measured on the oscilloscope, and it was found that the output of the loop filter was shorted to ground underneath the ADF7012 IC. The shorted trace was cut and the pin was connected using 30ga wire to the output of the loop filter. PLL operation was then verified using the R and N divider outputs on the MUXOUT pin. Trial and error showed that the power amplifier was enabled when setting the device to ASK mode with data inverted set (since the TxData and TxClock pins were grounded by design).

MSP430 Launchpad Shield

In order to facilitate testing with the ADF7012, a "shield" containing analog was built for the MSP430 Launchpad. The shield is based on APRSgen, a system based around the MSP430 Launchpad that I built while working at the Naval Postgraduate School during the Summer of 2011. APRSgen is a system that allows AX.25 packets at various baud rates to be assembled into bitstreams via a Python program, and output was audio or digital waveforms via the MSP430 and shield. The shield consists of three op-amps that adjust the cutoff frequency of a low-pass filter, and the gain and DC offset of the generated signal.

The ADF7012 shield contains all hardware of the APRSgen shield, and includes the ADF7012 test board itself, with a jumper to connect the analog signal to the VCXO control input. The schematic for the test board is shown below.

ADF7012 Shield Schematic


The spectra of the ADF7012 were captured for a carrier at 146MHz, the second through fourth harmonics, and an FM signal at 400 and 1000Hz, generated by the MSP430, at 400mVpp.

FM spectra of 400Hz (left, BW = 7.8kHz) and 1kHz (right, BW = 7.45kHz) tones at 400mVpp.

The spectra of the 400Hz tone (using the -3dB points) is kHz. The spectra of the 1kHz tone (using the -3dB points) is 7.8kHz.

Frequency (MHz) Power (dBm) Power (dBc)
146 10.23 0.00
292 -40.75 -50.98
438 -33.92 -44.15
584 -71.59 -81.82

The data shows that the 5th order low-pass filter keeps harmonics at least 4.15dB better than the FCC spec of -40dBc maximum power of spurious signals.[2] However, filtering after the power amplifier is still a concern, as the power amplifier will produce additional power at the harmonics. Below are the harmonic and carrier gains for the SKY65017 amplifier with a 0dBm input (20dB gain, 20dBm P1dB, 35dBm OIP3).

Frequency (MHz) Gain (dB)
146 18.58
292 48.66
438 52.10

Following the procedure used with the MICRF112 test board, a plot of the frequency vs. tuning voltage was obtained using an external power supply to bias the VCXO. The results show that the VCXO shows a nearly linear tuning curve, especially when biased between 1 and 2.5V. From this data, the proper voltage swing to generate a 4.8kHz deviation audio signal was determined to be 0.217Vpp.

Frequency vs. tuning voltage for the ADF7012 with Abracon 20MHz VCXO reference.

The output power vs. power level at 146MHz (set via the R2 register) was measured using a spectrum analyzer. The maximum power was 10.33dBm at 146MHz. Output power can be varied using the settings in the Programming section with GOOK set to 0.

Output power vs. power level for the ADF7012, measured at 146MHz.

The upper and lower ranges of the PLL (condition of phase noise < -20dBc) are approximately: 158MHz, 141.083MHz, yielding a total tuning range of 16.9MHz, just over the range needed to cover the 2m band + 10.7MHz for LO generation. However, in this case, the phase noise would be unacceptable in a receiver application. Reducing the VCO bias to a value of 5 (2.5mA), and the charge pump at maximum current (largest loop bandwidth) was determined experimentally to yield the lowest phase noise.


  1. Analog Devices, Inc., "ADF7012 Multichannel ISM Band FSK/GFSK/OOK/GOOK/ASK Transmitter," June 2009. [Online]. Available: [Accessed 5 February 2012].
  2. Federal Communications Commission, "Title 47, Part 97, Sec. 307 Emission Standards," Oct. 2000. Available: